VPI Simulation With Icarus Verilog On Linux

These instructions should work similar for any UNIX® like platform (or potentially Windows with Cygwin+Icarus) Some paths may need to be altered depending upon your system.

Requirements

Icarus Verilog
The compiler commands below expect veriuser.h in /usr/local/include

OpenCV Library
The paths below are assuming a default install of OpenCV in /usr/local/* If your install is in a different location, you will need to modify the include and link paths for the compiler.

C/C++ compiler
GCC works well and should be installed on your Linux system. If not, install your distribution's "C/C++ development" packages. I have not tested with the Intel C/C++ compiler, but should work.

Command Line Building the Sensor and Display libraries

Compile and link the sensor module

g++ -fPIC -c -o imageSensor.o imageSensor.cpp -I/usr/local/include/opencv
g++ -fPIC -shared -o imageSensor.vpi imageSensor.o -L/usr/local/lib -lcv -lhighgui

Compile and link the display module

g++ -fPIC -c -o imageDisplay.o imageDisplay.cpp -I/usr/local/include/opencv
g++ -fPIC -shared -o imageDisplay.vpi imageDisplay.o -L/usr/local/lib -lcv -lhighgui

Command Line Simulation with Icarus

Compile the Verilog files
iverilog -o imageSim sensor.v top.v -m ./sensor -m ./display

Run a simulation
You must find an image file and place it in the working directory as "image.jpg". (The file path is set as a parameter in the top.v file)
For the Icarus Verilog simulator, the above compile command will produce an executable file that *is* the simulation. Simply run the executable:
./imageSim
If you do not have an image file image.jpg in the current working directory, you will get a Segmentation fault.
After a brief period of time, a window should appear on the screen and your image should appear. Depending upon the speed of the simulation machine and size of the image, it may take several seconds to even a minute. Its best to try this first on a small image <= 640x480. On an 1.6GHz machine with a 640x480 input image, it will take around 20sec.

View wave-forms from the `testbench.vcd` file

Any vcd (Verilog change dump) file viewer should work. I've been using the GTKWave package. You must, however, place debug type $dumpvars() commands in your Verilog code to dump the wave-forms. There are two lines that, if un-commented, will create the testbench.vcd file and dump all the testbench signals. See just below the testbench() begining in top.v